1. Technical Field
The present invention relates in general to data processing systems and in particular to a processor (processor) in a data processing system. More particularly, the present invention relates to instruction operations within the processor.
2. Description of the Related Art
Complex processors have very little room for performance errors and typically must operate with little or no processing errors. During initial design stages of a complex processor, it is probable that program instructions will have to be modified to improve operations that have a direct effect on performance. Additionally, performance errors may be found, in the field in program designs after a processor has been installed.
Many complex processors utilize a reduced instruction set computer ("RISC") core processor which is generally characterized by high throughput of instructions. RISC processors usually operate at a high clock frequency and because of the minimal instruction set do so very efficiently. In addition to high clock speed, processor efficiency is improved even more by the inclusion of multiple execution units allowing the execution of two, and sometimes more, instructions per clock cycle.
Processors with the ability to execute multiple instructions per clock cycle are described as "superscalar." Superscalar processors, such as the PowerPC.TM. family of processors available from IBM Corporation of Armonk, N.Y., provide simultaneous dispatch of multiple instructions. Included in the processor are an Instruction Cache ("IC"), an Instruction Dispatch Unit ("IDU"), an Execution Unit ("EU") and a Completion Unit ("CU"). Generally, a superscalar, RISC processor is "pipelined," meaning that a second instruction is waiting to enter the execution unit as soon as the previous instruction is finished. A typical RISC instruction set (PowerPC.TM.) contains three broad categories of instructions: branch instructions (including specific branching instructions, system calls and Condition Register logical instructions); fixed point instructions and floating point instructions. Each group is executed by an appropriate function unit.
In a superscalar processor, instruction processing is usually accomplished in six stages--fetch, decode, dispatch, execute, completion and writeback stages. The fetch stage is primarily responsible for fetching instructions from an instruction cache and determining the address of the next instruction to be fetched. The decode stage generally handles all time-critical instruction decoding for instructions in an instruction buffer. The dispatch stage is responsible for non-time-critical decoding of instructions supplied by the decode stage and for determining which of the instructions can be dispatched in the current cycle.
The execute stage executes the instruction selected in the dispatch stage, which may come from the reservation stations or from instructions arriving from dispatch. The completion stage maintains the correct architectural machine state by considering instructions residing in a completion buffer and utilizes information about the status of instructions provided by the execute stage. The write back stage is used to write back any information from rename buffers that is not written back by the completion stage.
Complex processors, in this instance utilizing a RISC core, must perform with little or no margin for error. Instructions must be transformed into one or more internal operations (read hardware instructions) in the Instruction Decode Unit. At different stages between initial design and field experience, originally designed instruction operations in the processor may be changed because of unforeseen problems. Generally, the process requires a determination of the operation(s) that needs to be modified, a redesign of the hardware instructions and a reprogram of the processor. If errors are found in the field, the modification of the system is much more expensive in time and money. Generally, the processor must be changed out and any required support devices must be reprogrammed or changed out, contributing to an unnecessary expense in time and money. Furthermore, any advances made in the chip firmware currently requires that the chip be replaced.
It would be desirable therefore, to provide a method and apparatus that would allow for substituting instruction operations, both in the field and in the design stage, that would optimize performance and flexibility of a processor. It would also be desirable to provide a mechanism that would recognize incorrect instructions and enable correction of the instructions.